Tuning Stationary Iterative Solvers for Fault Resilience

TitleTuning Stationary Iterative Solvers for Fault Resilience
Publication TypeConference Paper
Year of Publication2015
AuthorsAnzt, H., J. Dongarra, and E. S. Quintana-Ortí
Conference Name6th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA15)
Date Published2015-11
PublisherACM
Conference LocationAustin, TX
AbstractAs the transistor’s feature size decreases following Moore’s Law, hardware will become more prone to permanent, intermittent, and transient errors, increasing the number of failures experienced by applications, and diminishing the confidence of users. As a result, resilience is considered the most difficult under addressed issue faced by the High Performance Computing community. In this paper, we address the design of error resilient iterative solvers for sparse linear systems. Contrary to most previous approaches, based on Krylov subspace methods, for this purpose we analyze stationary component-wise relaxation. Concretely, starting from a plain implementation of the Jacobi iteration, we design a low-cost component-wise technique that elegantly handles bit-flips, turning the initial synchronized solver into an asynchronous iteration. Our experimental study employs sparse incomplete factorizations from several practical applications to expose the convergence delay incurred by the fault-tolerant implementation.