Optimal Resilience Patterns to Cope with Fail-stop and Silent Errors

TitleOptimal Resilience Patterns to Cope with Fail-stop and Silent Errors
Publication TypeConference Paper
Year of Publication2016
AuthorsBenoit, A., A. Cavelan, Y. Robert, and H. Sun
Conference Name2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
Date Published05-2016
PublisherIEEE
Conference LocationChicago, IL
Keywordsfail-stop errors, multilevel checkpoint, optimal pattern, resilience, silent errors, verification
AbstractThis work focuses on resilience techniques at extreme scale. Many papers deal with fail-stop errors. Many others deal with silent errors (or silent data corruptions). But very few papers deal with fail-stop and silent errors simultaneously. However, HPC applications will obviously have to cope with both error sources. This paper presents a unified framework and optimal algorithmic solutions to this double challenge. Silent errors are handled via verification mechanisms (either partially or fully accurate) and in-memory checkpoints. Fail-stop errors are processed via disk checkpoints. All verification and checkpoint types are combined into computational patterns. We provide a unified model, and a full characterization of the optimal pattern. Our results nicely extend several published solutions and demonstrate how to make use of different techniques to solve the double threat of fail-stop and silent errors. Extensive simulations based on real data confirm the accuracy of the model, and show that patterns that combine all resilience mechanisms are required to provide acceptable overheads.
DOI10.1109/IPDPS.2016.39