Publications

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Conference Proceedings
London, K., S. Moore, P. Mucci, K. Seymour, and R. Luczak, The PAPI Cross-Platform Interface to Hardware Performance Counters,” Department of Defense Users' Group Conference Proceedings, Biloxi, Mississippi, June 2001.  (328.56 KB)
Browne, S., C. Deane, G. Ho, and P. Mucci, PAPI: A Portable Interface to Hardware Performance Counters,” Proceedings of Department of Defense HPCMP Users Group Conference, June 1999.  (57.77 KB)
Fürlinger, K., and S. Moore, OpenMP-centric Performance Analysis of Hybrid Applications,” Proc. 2008 IEEE International Conference on Cluster Computing (CLUSTER 2008), Tsukuba, Japan, January 2008.  (218.63 KB)
Supinski, B. R. de, S. Alam, D. Bailey, L. Carrington, C. Daley, A. Dubey, T. Gamblin, D. Gunter, P. D. Hovland, H. Jagode, et al., Modeling the Office of Science Ten Year Facilities Plan: The PERI Architecture Tiger Team,” SciDAC 2009, Journal of Physics: Conference Series, vol. 180(2009)012039, San Diego, California, IOP Publishing, July 2009.  (906.39 KB)
Moore, S., D. Arnold, and D. Cronk, Metacomputing Support for the SARA3D Structural Acoustics Application,” Department of Defense Users' Group Conference (to appear), Biloxi, Mississippi, June 2001.  (64.58 KB)
Shende, S., A. Maloney, S. Moore, and D. Cronk, Memory Leak Detection in Fortran Applications using TAU,” Proc. DoD HPCMP Users Group Conference (HPCMP-UGC'07), Pittsburgh, PA, IEEE Computer Society, January 2007.
Weaver, V. M., M. Johnson, K. Kasichayanula, J. Ralph, P. Luszczek, D. Terpstra, and S. Moore, Measuring Energy and Power with PAPI,” International Workshop on Power-Aware Systems and Architectures, Pittsburgh, PA, September 2012.  (146.79 KB)
Portillo, R., P. J. Teller, D. Cronk, and S. Moore, Making Performance Analysis and Tuning Part of the Software Development Cycle,” Proceedings of DoD HPCMP UGC 2009, San Diego, CA, IEEE, June 2009.
Wolf, F., F. Freitag, B. Mohr, S. Moore, and B. Wylie, Large Event Traces in Parallel Performance Analysis,” 8th Workshop 'Parallel Systems and Algorithms' (PASA), Lecture Notes in Informatics, no. ICL-UT-06-08, Frankfurt/Main, Germany, Gesellschaft für Informatik, March 2006.  (92.47 KB)
Song, F., S. Moore, and J. Dongarra, L2 Cache Modeling for Scientific Applications on Chip Multi-Processors,” Proceedings of the 2007 International Conference on Parallel Processing, Xi'an, China, IEEE Computer Society, January 2007.  (654.11 KB)
Moore, S., F. Wolf, J. Dongarra, and B. Mohr, Improving Time to Solution with Automated Performance Analysis,” Second Workshop on Productivity and Performance in High-End Computing (P-PHEC) at 11th International Symposium on High Performance Computer Architecture (HPCA-2005), San Francisco, February 2005.  (112.63 KB)
Song, F., S. Moore, and J. Dongarra, Feedback-Directed Thread Scheduling with Memory Considerations,” IEEE International Symposium on High Performance Distributed Computing, Monterey Bay, CA, June 2007.  (297.24 KB)
Dongarra, J., S. Moore, G. D. Peterson, S. Tomov, J. Allred, V. Natoli, and D. Richie, Exploring New Architectures in Accelerating CFD for Air Force Applications,” Proceedings of the DoD HPCMP User Group Conference, Seattle, Washington, January 2008.  (492.86 KB)
Song, F., J. Dongarra, and S. Moore, Experiments with Strassen's Algorithm: From Sequential to Parallel,” 18th IASTED International Conference on Parallel and Distributed Computing and Systems PDCS 2006 (submitted), Dallas, Texas, January 2006.  (514.33 KB)
Dongarra, J., K. London, S. Moore, P. Mucci, D. Terpstra, H. You, and M. Zhou, Experiences and Lessons Learned with a Portable Interface to Hardware Performance Counters,” PADTAD Workshop, IPDPS 2003, Nice, France, April 2003.  (432.57 KB)
Luszczek, P., E. Meek, S. Moore, D. Terpstra, V. M. Weaver, and J. Dongarra, Evaluation of the HPC Challenge Benchmarks in Virtualized Environments,” 6th Workshop on Virtualization in High-Performance Cloud Computing, Bordeaux, France, August 2011.  (114.73 KB)
London, K., J. Dongarra, S. Moore, P. Mucci, K. Seymour, and T.. Spencer, End-user Tools for Application Performance Analysis, Using Hardware Counters,” International Conference on Parallel and Distributed Computing Systems, Dallas, TX, August 2001.  (306.54 KB)
Wolf, F., B. Mohr, J. Dongarra, and S. Moore, Efficient Pattern Search in Large Traces through Successive Refinement,” Proceedings of Euro-Par 2004, Pisa, Italy, Springer-Verlag, August 2004.  (177.46 KB)
Fürlinger, K., and S. Moore, Detection and Analysis of Iterative Behavior in Parallel Applications,” Proceedings of the 2008 International Conference on Computational Science (ICCS 2008), vol. 5103, Krakow, Poland, pp. 261-267, January 2008.  (141.02 KB)
You, H., Q. Liu, Z. Li, and S. Moore, The Design of an Auto-tuning I/O Framework on Cray XT5 System,” Cray Users Group Conference (CUG'11) (Best Paper Finalist), Fairbanks, Alaska, May 2011.  (459.57 KB)
Fürlinger, K., and S. Moore, Continuous Runtime Profiling of OpenMP Applications,” Proceedings of the 2007 Conference on Parallel Computing (PARCO 2007), Juelich and Aachen, Germany, January 2007.  (408.01 KB)
Mucci, P., J. Dongarra, R. Kufrin, S. Moore, F. Song, and F. Wolf, Automating the Large-Scale Collection and Analysis of Performance,” In Proceedings of the 5th LCI International Conference on Linux Clusters: The HPC Revolution, Austin, Texas, May 2004.  (511.6 KB)
Bhatia, N., F. Song, F. Wolf, J. Dongarra, B. Mohr, and S. Moore, Automatic Experimental Analysis of Communication Patterns in Virtual Topologies,” In Proceedings of the International Conference on Parallel Processing, Oslo, Norway, IEEE Computer Society, June 2005.  (227.13 KB)
Song, F., F. Wolf, N. Bhatia, J. Dongarra, and S. Moore, An Algebra for Cross-Experiment Performance Analysis,” 2004 International Conference on Parallel Processing (ICCP-04), Montreal, Quebec, Canada, August 2004.  (166.12 KB)
Dongarra, J., S. Moore, P. Mucci, K. Seymour, and H. You, Accurate Cache and TLB Characterization Using hardware Counters,” Proceedings of ICCS 2004 (to appear), Krakow Poland, January 2004.  (167.1 KB)

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