A Performance Model to Execute Workflows on High-Bandwidth Memory Architectures

TitleA Performance Model to Execute Workflows on High-Bandwidth Memory Architectures
Publication TypeConference Paper
Year of Publication2018
AuthorsBenoit, A., S. Perarnau, L. Pottier, and Y. Robert
Conference NameThe 47th International Conference on Parallel Processing (ICPP 2018)
Date Published08-2018
PublisherIEEE Computer Society Press
Conference LocationEugene, OR
Abstract

This work presents a realistic performance model to execute scientific workflows on high-bandwidth memory architectures such as the Intel Knights Landing. We provide a detailed analysis of the execution time on such platforms, taking into account transfers from both fast and slow memory and their overlap with computations. We discuss several scheduling and mapping strategies: not only tasks must be assigned to computing resource, but also one has to decide which fraction of input and output data will reside in fast memory, and which will have to stay in slow memory. Extensive simulations allow us to assess the impact of the mapping strategies on performance. We also conduct actual experiments for a simple 1D Gauss-Seidel kernel, which assess the accuracy of the model and further demonstrate the importance of a tuned memory management. Altogether, our model and results lay the foundations for further studies and experiments on dual-memory systems.

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