%0 Conference Paper %B 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2021) %D 2021 %T Distributed-Memory Multi-GPU Block-Sparse Tensor Contraction for Electronic Structure %A Thomas Herault %A Yves Robert %A George Bosilca %A Robert Harrison %A Cannada Lewis %A Edward Valeev %A Jack Dongarra %K block-sparse matrix multiplication %K distributed-memory %K Electronic structure %K multi-GPU node %K parsec %K tensor contraction %X Many domains of scientific simulation (chemistry, condensed matter physics, data science) increasingly eschew dense tensors for block-sparse tensors, sometimes with additional structure (recursive hierarchy, rank sparsity, etc.). Distributed-memory parallel computation with block-sparse tensorial data is paramount to minimize the time-tosolution (e.g., to study dynamical problems or for real-time analysis) and to accommodate problems of realistic size that are too large to fit into the host/device memory of a single node equipped with accelerators. Unfortunately, computation with such irregular data structures is a poor match to the dominant imperative, bulk-synchronous parallel programming model. In this paper, we focus on the critical element of block-sparse tensor algebra, namely binary tensor contraction, and report on an efficient and scalable implementation using the task-focused PaRSEC runtime. High performance of the block-sparse tensor contraction on the Summit supercomputer is demonstrated for synthetic data as well as for real data involved in electronic structure simulations of unprecedented size. %B 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2021) %I IEEE %C Portland, OR %8 2021-05 %G eng %U https://hal.inria.fr/hal-02970659/document