Autotuning Batch Cholesky Factorization in CUDA with Interleaved Layout of Matrices

TitleAutotuning Batch Cholesky Factorization in CUDA with Interleaved Layout of Matrices
Publication TypeConference Paper
Year of Publication2017
AuthorsGates, M., J. Kurzak, P. Luszczek, Y. Pei, and J. Dongarra
Conference NameParallel and Distributed Processing Symposium Workshops (IPDPSW)
Date Published06-2017
PublisherIEEE
Conference LocationOrlando, FL
Keywordsbatch computation, Cholesky Factorization, data layout, GPU computing, numerical linear algebra
Abstract

Batch matrix operations address the case of solving the same linear algebra problem for a very large number of very small matrices. In this paper, we focus on implementing the batch Cholesky factorization in CUDA, in single precision arithmetic, for NVIDIA GPUs. Specifically, we look into the benefits of using noncanonical data layouts, where consecutive memory locations store elements with the same row and column index in a set of consecutive matrices. We discuss a number of different implementation options and tuning parameters. We demonstrate superior performance to traditional implementations for the case of very small matrices.

DOI10.1109/IPDPSW.2017.18
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